1. Field of the Invention
The present invention relates generally to non-volatile memory devices, and more particularly to methods for programming multi-level cells.
2. Description of Related Art
Non-volatile memory technology includes memory cells that store charge between the channel and gate of a transistor. The charge stored affects the threshold voltage level Vth of the transistor, and the threshold voltage level of the transistor due to the stored charge can be sensed to indicate data.
One type of charge storage memory cell is known as a floating gate memory cell. In a floating gate memory cell, source and drain regions are separated by a semiconductor channel region, a tunnel dielectric is formed over the channel, a floating gate of conductive material such as polysilicon is formed over the tunnel dielectric, and an inter-poly dielectric is formed over the floating gate to isolate it from the word line or control gate of the memory cell. The threshold voltage of the memory cell is changed by storing or removing charge on the floating gate by applying appropriate voltages to the control gate and the source and drain regions of the memory cell.
Another type of memory cell based on storing charge between the channel and gate of a field effect transistor uses a dielectric charge trapping structure. In this type of memory cell, a dielectric charge trapping structure is formed over a tunnel dielectric which isolates the dielectric charge trapping structure from the channel, and a top dielectric layer is formed over the charge trapping structure to isolate it from the word line or gate. A representative device is known as a silicon-oxide-nitride-oxide-silicon SONOS cell. The threshold voltage of the memory cell is changed by storing or removing charge on the charge trapping structure by applying appropriate voltages to the gate and the source and drain regions of the memory cell. Because the charge does not move through the non-conductive charge trapping layer, charge can be localized in more than one charge-trapping site within the charge trapping structure. See, for example, U.S. Pat. No. 7,110,300 which is incorporated by reference herein.
FIG. 1 is a graph of a distribution of single-level memory cells having one of two states (storing one bit of data), a low threshold erased state 100 and a high threshold programmed state 102 each having distinct threshold distribution ranges. The low state 100 and high state 102 may have distributions different from an initial distribution 110 of the memory cells prior to performing programming operations.
The low threshold state 100 has a maximum threshold voltage that can be defined as an erase verify voltage VEV. The high threshold state 102 has a minimum threshold voltage that can be defined as a program verify voltage VPV. In practice the erase verify voltage VEV may be slightly higher than the maximum of the low state 100, and the program verify voltage VPV may be slightly lower than the minimum of the high state 102.
The difference between the program verify voltage VPV and the erase verify voltage VEV defines a read window 101 used to distinguish cells in the low state 100 from cells in the high state 102. The state of a memory cell can be determined by measuring whether the threshold of the memory cell is above or below a predetermined threshold voltage value within the read window 101.
Multi-level memory cells have been developed that can store more than two states, thereby increasing the storage density of the memory cells and providing an efficient technique for reducing die size. FIG. 2 is a graph of a distribution of multi-level memory cells in one of four states (storing two bits of data). The threshold states 200 (zero level), 202 (first level), 204 (second level), and 206 (third level) each have distinct threshold distribution ranges separated by read windows 201, 203, and 205.
The zero level threshold state 200 has a maximum threshold voltage that can be defined as an erase verify voltage VEV. The first level threshold state 202 has a minimum threshold voltage that can be defined as a first level program verify voltage VPV1, the second level threshold state 204 has a minimum threshold voltage that can be defined as a second level program verify voltage VPV2, and the third level threshold state 206 has a minimum threshold voltage that can be defined as a third level program verify voltage VPV3.
In order to reliably distinguish between the various states in a multi-level memory cell, accurate control of the amount of charge stored in the memory cell is important. To accurately control the amount of charge stored, program-and-verify methods for programming multi-level memory cells are widely used and involve programming the memory cell in a ramped or step-wise fashion. These methods include an iterative process of performing a programming step followed by a verification step in order to determine whether the desired threshold level of the memory cell has been achieved. Problems with these methods include a slow programming speed since the bias voltages for the initial programming step must be conservatively selected so as to prevent programming the memory cell to an incorrect state. Using such conservatively selected bias voltages for the initial programming step results in a number of programming and verification steps being performed, resulting in a slow programming speed of the memory cell.
Accordingly, it is desirable to have a multi-level memory cell programming method that can determine initial bias voltages such that the programming time of a memory cell is reduced.